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rev. 1. 0 n o v e m b e r 2011 page 1 of 16 www.aosmd.com aoz1977 - 1 high voltage led driver ic general description the aoz1977 - 1 is a high - efficiency led driver controller for high voltage led backlighting applications. it is designed to drive high - brightness led light bar in led tv applications. the aoz1977 - 1 can support a wide range of input and output voltages. the input bias voltage of aoz1977 - 1 is from 8v to 30v. the aoz1977 - 1 has multiple features to protect the regulator under fault conditions. a control pin can disable an external switch to disconnect the leds current path from the output in pwm dimming or under catastrophic failure conditions. cycle - by - cycle current protection limits the peak inductor current. thermal shutdown provides another level of protection. low feedback voltage (500mv) helps reduce power loss. the aoz1977 - 1 features sync function to allow for synchronization with external clock or multiple aoz1977 - 1 . the aoz1977 - 1 is available in a standard so - 16 package and operates over the temp erature range of - 40 c to +85 . features ? 8v to 30v input bias v oltage ? up to 16v driving capability at gate pin and dpwm pin. ? disconnect control pin for pwm dimming or fault conditions. ? bi - directional clock synchronization ? 500mv feedback regulation ? f eedback short protection ? 8 bit pwm dimming resolution ? cycle - by - cycle current limit ? output over - voltage protection ? led short and open protection ? thermal shutdown protection ? so - 16 package applications ? lcd tv led backlight ? led monitor ? general led lighting typical application
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 2 of 16 aoz1977 - 1 ordering information part number temperature range package environmental aoz1977ai - 1 - 40c to +85c so ic - 16 green aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. pin configuration soic - 16 ( top view ) pin description part number pin name pin function 1 vin input supply pin. 2 vdd internal 8v linear regulator output pin for gate driver. connect a minimum 0.22f ceramic capacitor from vdd to ground. 3 gate external boost nmos gate controller pin. connect to the gate of external nmos switch. 4 gnd ground pin. 5 cs nmos switch current sense pin. 6 timer sets feedback short protection blanking time at start up. connect c timer to gnd 7 osc frequency set pin. connect r osc to ground via a resistor to set the switching frequency. 8 sync frequency synchronous pin. connect sync to external clock for desired switching frequency or connect to multiple controllers for phase locked frequency synch ronization. 9 ilim current limit set pin. 10 vref reference voltage. 11 dpwm fault and dimming control output pin. dpwm=high for led connect. dpwm=low for led disconnect. connect to the gate of external nmos switch. 12 ovp over - voltage feedback input pin . use a voltage divider to set the boost regulator output over - voltage protection threshold. 13 dbrt pwm brightness control input. dbrt controls the led brightness by turning the led on and off using a pwm signal. the brightness is proportional to the pwm duty cycle. 14 comp compensation pin. comp is the output of the internal error amplifier. for loop compensation connect a rc network from comp to ground. 15 iset led current set pin. connect iset to vref resistor divider to set the led current level. 16 fb feedback input pin. connect to sense resistor at led string. vin vdd gate gnd cs timer osc syn c fb ise t comp dbrt ovp dpwm vref ilim 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
aoz1977 - 1 page 3 of 16 rev. 1. 0 n o v e m b e r 2011 www.aosmd.com pin functions pin1: vin this is the input power for the controller ic. if the input of the boost converter is less than 30v, vin can be connected directly to the boost supply voltage. if the boost supply voltage is higher than 30v, a separate supply rail between 8v to 30v is required for the vin pin. it is recommended that an rc filter should be added between vin and boost supply voltage if they are connected directly. please note that when vin is not directly connected to the boost supply voltage , proper power up sequence will be required. boost supply voltage must be ready before powering up vin . there is no power down sequence required. pin2: vdd this is the output of an internal 8v regulator. it requires a 2.2 f decoupling capacitor to be connec ted to ground. t he internal regulator can be over - driven by external supply between 8v to 16v if higher gate drive is desired . pin3: gate this is the driver out put for the gate of boost n mos switch. the gate = high voltage is equal to vdd voltage. it is r ecommended to add a 1 resistor between this pin and the nmos gate. the resistor value can be optimized depending on the switching frequency and selection of the nmos switch. pin4: gnd this is the signal and power g round for the ic controller . it is recom mended that all the low current paths are connected to this pin as close as possible to the ic controller. it is not recommended to connect any output or input filter capacitors and any current sense resistors to this pin directly . the ic controller ground should be an island around the ic connected to the pwr gnd at a single point in the layout. pin5: cs this is the input for peak current sense. this pin serves the functions of current feedback , peak current limit detection, and fault current detection . the pin current limit is set by the voltage defined at pin9 ilim . the current limit is defined as voltage at ilim divided by the sense resistor connected from this pin to ground. if cs pin detect a fault current detection such as short circuit condition, it will trigger a fault signal. the ic controller will latch - off until vin is toggled. pin6: timer startup - short protection timer. connecting this pin to gnd via a capacitor , sets the time the controller allows feedback voltage to remain below 0.19v durin g start up. if voltage at fb remains below 0.19v after set time has expired , the controller will shut down and latch off. after the power - up sequence is completed, the timer pin will have no effect. the controller will instantaneously latch - off whenever f eedback voltage drops below 0.19v. for most designs i t is recommended to use no less than 100nf capacitor. a c timer timer p 25 . 1 / note that dbrt must be applied before c timer times out. pin7: rosc this is the pin to select the switching frequency for the boost controller. a resistor should be connected between this pin to ground. the switching frequency is determined by the following equation: pf r f osc sw 10 / 1 u : it is recommended that the switching frequency for normal operation should be between 50kh z to 350khz. pin8: sync this is a bidirectional pin for oscillator clock synchronization. clock synchronization will choose either the internal clock or the external clock through this pin, whichever is faster. the faster external clock must be ready befo re power is applied to this ic controller. if the internal clock is faster, the sync pin will have the same frequency as the internal clock. when multiple ic controllers are used in the design, it is recommended to connect all sync pins together. this will reduce the interference of ?beat? frequencies associated with multiple switching frequencies.
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 4 of 16 aoz1977 - 1 pin9: ilim this is the current limit set point . the voltage at this pin will determine the cs current limit threshold detected at pin5 cs . the voltage can be derived from a resistor divider from the 1.2v reference voltage at pin10 vref . to minimize power consumption, it is recommended that the total resistance for the divider is approximately 20k?. pin10: vref this is a 1.2v voltage reference for all external bias. this reference voltage can be used for pin15 iset and pin9 ilim bias. pin11: dpwm this is the driver output for the gate of the led current control nmos switch. dpwm = low if pin13 dbrt signal is low or fault condition is triggered. the dpwm = high if pin13 dbrt signal is high under normal operation. the high voltage is equal to vdd voltage. it is recommended to add a 1? resistor between this pin and the nmos gate. the resistor value can be optimized depending on the switching frequency and selection of the nmos. pin12: ovp this is the input for led over - voltage protection. ovp monitors the led output voltage through a resistor divider. when the voltage at this pin is higher than 1v, the controller will stop switching immediately until vin power is toggled. pin13: dbrt this is the input for digital brightness control . a pwm logic signal is applied to this pin to vary the brightness of the led. the brightness of the led is proportional to the duty cycle of the pwm logic signal. the input signal will control the output driver at dpwm pin. this input pin cannot be left floating. power up sequencing is important. dbrt logic must be high before vin is higher than uvlo threshold. pin14 : comp t his is for feedback loop compensation . it is the output of the error amplifier that controls pwm logic for the boost controller. an rc network should be used to generate the compensation for boost feedback loop. pin15: i set this is for full scale led current setting. a reference voltage between 0.5v and 0.8v should be applied to this pin. the voltage can be derived from a resistor divider from the 1.2v reference voltage at pin10 vref . to minimize power consumption, it is recommended that the total resistance for the divider is approximately 20k?. the fb voltage will regulate to this voltage level. the full scale led current is derived by the fb voltage divided by the sense resistor. pin16: fb this is the feedback input for boost cont roller. this pin should connect to a resistor that senses the led current. the fb voltage will be regulated to iset voltage to determine the desired led current when led current control nmos switch is on. if the fb voltage drops below 0.19v the controller interprets this condition as either shorted fb sense resistor or led cathode shorted to gnd or output shorted to gnd and will immediately shutdown and latch off .
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 5 of 16 aoz1977 - 1 functional block absolute maximum ratings exceeding the absolute maximum ratings may damage the device. parameter rating vin to gnd - 0.3v to +32v gate, faultb to gnd - 0.3v to +16 v vdd to gnd - 0.3v to +16 v pwmdim, osc, iset , comp, fb timer, sync, cs. ilim, vref, ovp, to gnd - 0.3v to +6 v storage temperature (t s ) - 65c to +150c esd rating (1) 2kv note: 1. devices are inherently esd sensitive, handling precautions are required. human body model rating: 1.5k in series with 100pf. recommended operating ratings this device is not guaranteed to operate beyond the recommended operating ratings. parameter rating supply voltage (v vin ) 8v to 30v ambient temperature (t a ) - 40c to +85c package thermal resistance soic - 16 ( 4 ja ) 105c/w
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 6 of 16 aoz1977 - 1 electrical characteristics t a = 25c, v in = 24v unless otherwise specified. symbol parameter conditions min. typ. max units v vin vin supply voltage 8 30 v i vin _ on vin quiescent current not switching 2 ma v uvlo_rise v uvlo_fall vin uvlo threshold vin rising vin falling 6.2 7 6.5 7.3 v v vin _ hys vin uvlo hysteresis 500 mv v vdd vdd regulation voltage 8.5v < v vin < 30v 7.5 8 8.5 v oscillator f sw switching frequency r osc = 1m? r osc = 285k? 85 298 100 350 115 402 khz t on minimum on time (pwm) r osc = 1m? 150 200 ns gate driver i gate_source source current gate = 0v. vdd = 8v 200 250 ma i gate_sink sink current gate = 8v. vdd = 8v 400 450 ma t gate_rise rise time c gate = 1nf. vdd = 8v 10% to 90% of vdd 50 85 ns t gate_fall fall time c gate = 1nf. vdd = 8v 90% to 10% of vdd 25 45 ns inputs i cs cs input current cs = 0.3v 5 a i iset iset input current iset = 0.5v 5 a i ilim ilim input current ilim = 0.4v (140% of cs) 5 a i dbrt dbrt input current dbrt = 5v 5 a i ovp ovp input current ovp = 1.2v 5 a i fb fb input current fb = 0.5v 5 a f dbrt dbrt dimming frequency pwm minimum on time >9s 100 2000 hz outputs i vref vref output source current r vref = 6k? to gnd 200 a v vref vref reference voltage r vref = 6k? to gnd 1.188 1.2 1.212 v protection v ilim current limit set cs = 0.3v 126 133 140 % of v cs v ovp ovp threshold voltage 0.9 1 1.1 v v ovp_hys ovp hysteresis 200 mv i timer timer charge current 1.25 a t thermal_sd thermal shutdown threshold 145 c t thermal_hys thermal shutdown hysteresis 35 c dpwm drive i dpwm_source dpwm source current gate = 0v 36 ma i dpwm_sink dpwm sink current gate = 8v 46 ma logic input v dbrt_hi dbrt logic high 2.0 v v dbrt_lo dbrt logic low 0.8 v
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 7 of 16 aoz1977 - 1 typical performance characteristics switching waveforms of gate, inductor current and lx voltage: v led = 2 00 v, iled = 200ma pvin = 90v pvin = 150v pvin = 120v pvin = 100v gate (10v/div) inductor current (0.5a/div) lx voltage (100v/div) gate (10v/div) inductor current (0.5a/div) lx voltage (100v/div) gate (10v/div) inductor current (0.5a/div) lx voltage (100v/div) gate (10v/div) inductor current (0.5a/div) lx voltage (100v/div) 5 s/div 5 s /div 5 s /div 5 s/div
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 8 of 16 aoz1977 - 1 pwm dim waveforms: v in = 100 v , 200v led / 200ma , dbrt = 400hz dbrt = 10% zoomed dbrt = 0.5% dbrt = 90% dbrt = 50% led led current (0.2a/div) voltage (50v/div) dbrt (2v/div) led led current (0.2a/div) voltage (50v/div) dbrt (2v/div) led led current (0.2a/div) voltage (50v/div) dbrt (2v/div) led led current (0.2a/div) voltage (50v/div) dbrt (2v/div) 2 s /div 1ms/ div 1ms /div 1ms /div
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 9 of 16 aoz1977 - 1 additional waveforms pvin = 100v , v led = 2 00 v, iled = 200ma, fsw = 1 00khz feedback short protection during start-up feedback short protection during steady state lx voltage (100/div) (0.5vdiv) led current led voltage (100v/div) (200ma/div) partial led string short protection 1ms/div 1ms/div 50ms/div 100s/div ovp protection feedback voltage lx voltage (100/div) (0.5vdiv) led current led voltage (100v/div) (200ma/div) feedback voltage lx voltage (100/div) led current (100ma/div) led voltage (50v/div) lx voltage (100/div) (1vdiv) led current (100ma/div) feedback voltage
aoz1977 - 1 page 10 of 16 rev. 1 . 0 n o v e m b e r 2011 www.aosmd.com detailed description the aoz1977 - 1 is a boost dc/dc controller designed to power a series of leds by regulating the current into an led string. the led current information is provided to the system through the sense resistor rfb at the bottom of led string, between fb and gnd pins. protection features over - current protection at boost switch the current limit is a function of rs resistor value at cs pin and the voltage setting at ilim pin. the voltage at ilim is directly compared to the sense voltage at cs pin. when cs voltage reaches ilim set voltage, current limit protection triggers and the boost switch will be turned off immediately until the next clock cycle. to make sure that current limit protection does not affect the normal operation, the current limit should be set at least 3 0% higher than the inductor peak current. however, the voltage at ilim must be less than 0.4v. when cs voltage is higher than 0.4v, fault detection is active and it might affect the normal operation. ilim voltage is generated by connecting a resistor di vid er (rl1 and rl2 in typical application diagram) from 1.2v vref pin to ilim and gnd pins. to minimize power consumption, it is recommended that the total resistance for the divider is approximately 20k?. for example : if peak current is 0.55a. 30% higher is 0.72a. cs voltage is 0.72 a * 0.55? = 0.4v. over - voltage protection at output over - voltage protection is monitoring the led output voltage through a resistor divider (rov1 and rov2 in typical application circuit) from vout to ovp and gnd pins. when the vol tage at this pin is higher than 1v, the controller will stop switching immediately and will latch off until vin is recycled. led short protection when fb voltage exceeds 1v, the system will consider some or all leds are shorted instantaneously. under thi s condition, the controller will latch off until vin is recycled. led open protection when all leds are open, the system will respond by boosting the output voltage. once the output voltage reaches the ovp threshold, ovp protection will trigger, controlle r will latch off until vin is recycled. feedback short aoz1977 - 1 also protects against shorted feedback sense resistor or led cathode shorted to gnd. the controller will latch off when feedback voltage drops to 0.19v or below . thermal protection an inte rnal temperature sensor monitors the junction temperature. it shuts down the internal control circuit and all drivers if the junction temperature exceeds 145oc.
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 11 of 16 aoz1977 - 1 application information inductor selection inductor choice will be affected by many parameters, like duty cycle based on input/output setting, switching frequency, full scale led current level, and mode of operations. boost controller can operate under discontinuous mode, continuous mode, or critical conduction mode. for high voltage boos t led driver applications, it is recommended to use critical conduction mode for good stability and best efficiency. inductor current in critical conduction mode in out out in v i v i current input = = _ in critical conduction mode : in peak i di il = = 2 the duty cycle for the b oost dc/dc system is defined as: out min in out v v v d cycle duty ) ( _ ? = = to determine t he on time for the boost switch: sw f d dt time on = = _ for the application with vin=1 0 0 v, vout=200v, led current=200ma: a v a v i in 44 . 0 90 2 . 0 200 = = a a di 89 . 0 44 . 0 2 = = 55 . 0 200 90 200 = ? = v v v d the inductor value is determined by : h a v s di v dt l in 560 88 . 0 90 5 . 5 = = = after the inductor value is calculated, we need to c onsider the dc r resistan ce and the isat saturation current of the inductor. inductor dcr is inversely proportional to the isat. it is recommended to select an inductor for which the isat value should be at least 50% higher than the ilpeak value. to minimize emi effect, it is always preferable to use shielded type inductors. diode selection it is recommended to use fast recovery diode for d1. for most applications, schottky diodes with correct current and voltage rating are suitable. the diode current rating should be at least higher than the full scale led current. the diode voltage rating should be higher than the ovp l evel of vout voltage. output capacitor s the amount and type of capacitor used is mainly determined by the design output ripple (v ripple ) requirement : sw ripple out out f d v i c = when selecting output capacitors, it is more important to check the effective esr of the capacitor than the actual capacitance value. for examples, a 10 f fdsdflwru zlwk ? (65 zloo kdqgoh kljkhu ulssoh current but produce less output ripple than a 33 f fdsdflwru zlwk ? (65 ,w lv uhfrpphqghg wr xvh low esr mlcc ceramic capacitor s. for high voltage cost effective application, multiple electrolytic capacitors in parallel will reduce the total effective esr. input capacitors the input capacitors for boost converters do not require low esr due to the fact that the input current is c ontinuous. also, they do not contain large peak current as compared to the output capacit ors. t he ripple current at the input capacitor is: ( ) a v l f v v v i out sw in out in ripple in 17 . 0 3 . 0 _ = ? = w here , f sw is the switching frequency, 100khz in this example. electrolytic capacitors should work well with the appropriate voltage and ripple current rating, it is not recommended to use tantalum capacitors because boost converters do exhibit high surge currents during startup which can cause tantalum capacitors to fail. il peak
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 12 of 16 aoz1977 - 1 current sense r esistor s there are two current sense resistors in this application, an led current sense resistor rfb and a boost switch current sense resistor rs. rfb led current sense resistor is set by : ? = = = 5 . 2 2 . 0 5 . 0 _ _ a v current led voltage iset rfb led current is a function of iset voltage and rfb resistance. iset voltage is generated by connecting a resistor di vider (rr1 and rr2 in typical application diagram) from 1.2v vref pin to iset and gnd pins. to minimize power consumption, it is recommended that the total resistance for the divider is appro [lpdwho\n? rs boost switch current sense resistor is set by : ? = = = 375 . 0 8 . 0 3 . 0 _ _ 3 . 0 a v current peak inductor v rs for typical application, we recommend to set the voltage at cs to approximately 0.3v when inductor current reaches the peak, and 0.4v at ilim pin set by r11 and r12 div ided from 1.2v vref. boost feedback loop compensation the aoz1977 - 1 employs peak current mode control for easy use and fast transient response. peak current mode control eliminates the double pole effect of the output l&c filter. it greatly simplifies t he compensation loop design. with peak current mode control, the boost power stage can be simplified to be a one - pole, one left plane zero and one right half plane (rhp) system in frequency domain. the pole is dominant pole and can be calculated by: l o p r c f = 2 1 1 the zero is a esr zero due to output capacitor and its esr can be calculated by: co o z esr c f = 2 1 1 w here , c o is the output filter capacitor , r l is load resistor value, and esr co is the equivalent series resistance of output capacitor. the rhp zero has the effect of a zero in the gain causing an imposed +20db/decade on the roll off, but has the effect of a pole in the phase, subtracting 90 o in the phase. th e rhp zero can be calculated by: o o in z v i l v f = 2 2 2 the rhp zero ob viously can cause the instable issue if the bandwidth is higher. it is recommended to design the bandwidth to lower than the one half frequency of rhp zero. the compensation design is actually to shape the converter close loop transfer function to get des ired gain and phase. several different types of compensation network can be used for aoz1977 - 1 . for most cases, a series capacitor and resistor network connected to the comp pin sets the pole - zero and is adequate for a stable high - bandwidth control loop. in the aoz1977 - 1 , fb pin and comp pin are the inverting input and the output of internal transconductance error amplifier. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: vea c ea p g c g f = 2 2 w here , g ea is the err or amplifier transconductance, which is a - 6 a/v, g vea is the error amplifier voltage gain, which is 1 0 0 0 v/v, and c c is compensation capacitor. the zero given by the external compensation network, capacitor c c and resistor r c , is located a t: c c z r c f = 2 1 2 choosing the suitable c c and r c by tradi ng - off stability and bandwidth.
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 13 of 16 aoz1977 - 1 p cb layout consideration correct layout practices are essential for a working design that will meet expectations. it is recommended to use two - layer board for the design. however, a single layer board would be sufficient if basic layout rules are followed . in any smps layout, external components should be grouped into power or ic control. from typical application circuit, there are two gnd symbols. the strip ed one is for power gnd and the solid one is for signal/control gnd. both symbols are connected to a single point connection on the layout . all p ower connections should be as short and wide as possible in order to reduce undesired parasitic inductance. the o u tput capacitors should be physically placed in the current path between the smps and the load. input capacitors should be placed as close as possible to the input side of the inductor. to prevent interference and system noise , it is critical that the sw itch node connection for boost switch , inductor , and output diode must be as short and close as possible . a gnd copper layer covers the top layer to help shield the noise . for two - layer board, it is essential that the gnd plane under this switching node sh ould be filled and uninterrupted single p oint connection: c onnecting pwr gnd and signal gnd
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 14 of 16 aoz1977 - 1 package dimensions, soic - 16l notes: 1. all dimensions are in millimeters. 2. dimensions are inclusive of plating 3. package body sizes exclude mold flash and gate burrs. mold flash at the non-lead sides should be less than 6 mils. 2. dimension l is measured in gauge plane. 3. tolerance is 0.10mm unless otherwise specified. 4. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. symbols a a1 a2 b c d e1 e e l recommended land pattern min. 1.35 0.10 ? 0.33 0.19 9.80 3.80 5.80 0.40 0 nom. 1.60 ? 1.45 ? ? ? 3.90 1.27 typ 6.00 ? ? max. 1.75 0.25 ? 0.51 0.25 10.00 4.00 6.20 1.27 8 symbols a a1 a2 b c d e1 e e l min. 0.053 0.004 ? 0.013 0.007 0.386 0.150 0.228 0.016 0 nom. 0.063 ? 0.057 ? ? ? 0.154 0.050 typ 0.236 ? ? max. 0.069 0.010 ? 0.020 0.010 0.394 0.157 0.244 0.050 8 .004"(0.10mm) 16 3 2 1 2.2 0.63 1.27 2.87 5.74 0.8
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 15 of 16 aoz1977 - 1 tape and reel dimensions, soic - 16l uni t : mm uni t : mm feeding direction section a--a a a l c d0 p2 p0 p1 a0 e2 e e1 d1 max. ?332 ?13.0 0.2 10.1 min. 2.2 ty p . 22.4 max. 16.4 ?100.0 2.0 w3 h 2 w k s w1 n m 16mm t ape size 15.9~19.4 s m n (hub dia.) w3 (include flange distortion at outer edge) w1 (measured at hub) w2 (measured at hub) h k 2.0 0.5 t t b0 t k1 k0 0.3 0.05 2.0 0.1 8.00 0.1 4.0 0.1 7.50 0.1 1.75 0.1 16.00 0.3 t p2 p1 p0 e2 e1 e package so16 (16 mm) a0 6.50 0.1 b0 0.1 10.30 k0 0.1 2.30 d0 1.55 0.05 d1 1.6 0.1 b 1 b 2 a1 b1 b2 re f . 6.6 re f . 1.5 a1 re f . 3.5 1.80 0.1 k1 trailer tape 300mm min. components tape orientation in pocket leader tape 500mm min.
rev. 1. 0 n o v e m b e r 2011 www.aosmd.com page 16 of 16 aoz1977 - 1 part marking this datasheet contains preliminary data; supplementary data may be published at a later date. alpha and omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products are not authorized for use as critical components in life support devices or systems. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. aoz1977ai-1 (soic-16) z1 97 7a i-1 fx part number code assembly lot code year & week code lt yw fab & assembly location

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